In semiconductor manufacturing, a fabricated integrated circuit (IC) device is typically assembled into a package to be utilized on a printed circuit board as part of a larger circuit. In order for the leads of the package to make electrical contact with the bonding pads of the fabricated IC device, a metal bond (e.g., wire bond) is formed to make a connection between the bonding pad of the IC device and a lead extending to the package lead frame. In other configurations, such as a controlled collapse chip connection (C4), a solder ball connection is made to a ceramic or polymeric chip carrier.
In conventional wire-bond and C4 techniques, it is common to use a terminal metal (TD) aluminum pad structure between the wire in the uppermost wiring level (e.g., the terminal wire) and the wire-bond attachment or C4 ball attachment. However, the TD pad metal process involves an increased number of manufacturing steps and costs associated with the semiconductor structure. It is thus desirable to eliminate the aluminum TD pad. As such, a significant amount of research and development effort has been dedicated to the elimination of the TD layer for advanced back end of the line (BEOL) processing in an attempt to save processing costs.
In addition to bond pads, IC devices commonly include thin film resistors that are generally fabricated during BEOL processing. BEOL thin film resistors (such as tantalum nitride (TaN)) may be used to provide near-zero 1/f noise, and offer resistances that are better defined than corresponding resistors formed by diffusion into the semiconductor substrate. Additionally, resistors formed in the back end will have less parasitic capacitive coupling to the semiconductor substrate than resistors formed in the front end.
However, in current practice, the BEOL thin film resistors and TD-less bond pads are fabricated separately. Moreover, when plural devices in the uppermost wiring level each require a thin film resistor, separate processes are employed to form the respective thin-film resistors for each device. This separate fabrication results in an increased number of processing steps, which eliminates any possible realization of process cost savings that might be achievable by merely eliminating the aluminum TD pad.
Copper (Cu) interconnects are commonly used for on-chip wiring, because of low resistivity and long electromigration lifetime compared to other metals (e.g., Aluminum). However, as device dimensions shrink, the current density through the wires increases (especially in power busses), and the electromigration lifetime of Cu is no longer sufficient. Electromigration is a well known phenomena in which, generally speaking, atoms of a metal feature (e.g., wire, interconnect, via, etc.) are displaced due to the electrical current passing through the feature. The migration of atoms can result in voids in the feature, which can increase electrical resistance or cause failure of the feature, both of which negatively impact reliability of the integrated circuit.
It is common to use a refractory metal capping layer which can improve the electromigration lifetime of Cu. For example, CoWP (e.g., deposited selectively using electroless deposition) can improve the electromigration lifetime of Cu by over one hundred times than that of uncapped Cu. However, the selective deposition process used to form such capping layers are difficult to control, and leakage is often observed between neighboring lines due to inadvertent metal deposition on the dielectric.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.